FIG. 2 shows a conventional cascade current Miller circuit. The cascade current Miller circuit shown in FIG. 2 has a structure such that p-channel MOS transistors P10 and P12 forming a pair of current Miller circuits and p-channel MOS transistors P11 and P13 forming a pair of current Miller circuits are connected in cascade with each other. Of these pairs of current Miller circuits, the sources of the pair of current Miller circuits at the upper level (a first pair of current Miller circuits) are connected to a power supply voltage. Drain of the p-channel MOS transistor P11, that is the drain of one transistor of the two transistors forming the pair of current Miller circuits at the lower level (a second pair of current Miller circuits), is connected to a constant current source 9 that supply a constant current i.
Further, this cascade current Miller circuit has a structure such that n-channel MOS transistors N10 and N12 forming a pair of current Miller circuits and n-channel MOS transistors N11 and N13 forming a pair of current Miller circuits are connected in cascade with each other, to form a cascade Miller circuit. Drain of the n-channel MOS transistor N10, that is the drain of one transistor of the two transistors forming the pair of current Miller circuits at the upper level (a third pair of current Miller circuits), is connected to the drain of the p-channel MOS transistor P13. Thus the drain of the n-channel MOS transistor N10 is connected to the drain of other transistor of the second pair of current Miller circuits. The sources of the pair of current Miller circuits at the lower level (a fourth pair of current Miller circuits) are connected to the ground. Further, the drain of the n-channel MOS transistor N12, that is the drain of other transistor of the third pair of current Miller circuits, is connected to a drain of a p-channel MOS transistor P15. The p-channel MOS transistor P15 and a p-channel MOS transistor P14 are cascade-connected and their sources are connected to a power supply voltage.
In the above-described structure, a current path (PASS12) is formed by the p-channel MOS transistors P14 and P15 and the n-channel MOS transistors N12 and N13, and a current path (PASS10) is formed by the p-channel MOS transistors P10 and P11. Further, a current path (PASS11) is formed by the p-channel MOS transistors P12 and P13 and the n-channel MOS transistors N10 and N11. Reference symbols shown at the bottom of the drawing indicate channel lengths (hereinafter to be referred to as L-size) and channel widths (hereinafter to be referred to as W-size) of the respective MOS transistors. Sizes within each bracket indicate L-size and W-size respectively. It is assumed that there is a relationship of PL12&gt;PL13 and NL11&gt;NL10.
The operation of the cascade current Miller circuit will be explained below. At first, in FIG. 2, in the third and fourth current Miller circuits, there is a relationship that the W-size of the n-channel MOS transistor N12 is n times the W-size of the n-channel MOS transistor N10, and the W-size of the n-channel MOS transistor N13 is n times the W-size of the n-channel MOS transistor N11. Accordingly, the current flowing through the current path (PASS12) is expressed as i*n by the current Miller transfer of a current i from the current path (PASS11).
As shown in the drawing, a potential between the gate and the source (V.sub.GS10) and a potential between the drain and the source (V.sub.DS10) are equal, in the n-channel MOS transistor N10 that is the origin of the current Miller transfer. Similarly, in the n-channel MOS transistor N11, a potential between the gate and the source (V.sub.GS11) and a potential between the drain and the source (V.sub.DS11) are equal.
Accordingly, a potential between the gate and the source (V.sub.GS13) has a relationship that V.sub.GS13 =V.sub.GS11 =V.sub.DS11 in the n-channel MOS transistor N13 that is a current Miller transfer destination. Also, a potential between the gate and the source (V.sub.GS12) has a relationship that V.sub.GS12 =V.sub.G12 -V.sub.S12 =V.sub.GS11 +V.sub.GS10 -V.sub.DS13 in the n-channel MOS transistor N12. V.sub.G12 and V.sub.S12 respectively represent a gate potential and a source potential of the n-channel MOS transistor N12.
The following relationship is generally established in the saturation area of a MOS transistor. EQU V.sub.GS =SQRT(.alpha.IL/W)+V.sub.TH
where V.sub.GS, I, L, W and .alpha. respectively represent a voltage between the gate and the source, a drain current (I.sub.DS), L-size and W-size, and a constant.
When .DELTA. is substituted for SQRT (.alpha.IL/W), the following 10 relationship is established. ##EQU1##
.DELTA..sub.10, .DELTA..sub.11, .DELTA..sub.12 and .DELTA..sub.13 respectively represent the above .DELTA. in the n-channel MOS transistors N10, N11, N12 and N13. V.sub.TH10, V.sub.TH11, V.sub.TH12 and V.sub.TH13 respectively represent the above V.sub.TH in the n-channel MOS transistors N10, N11, N12 and N13.
In order for the above-described third and fourth pairs of current Miller circuits to operate normally, it is necessary that each MOS transistor always operates in the saturation area. In order for the MOS transistor to operate in the saturation area, it is necessary to satisfy the relationship V.sub.DS.gtoreq.V.sub.GS -V.sub.TH. Further, as the relationship of V.sub.GS =V.sub.TH +.DELTA. is established in the saturation area as described above, in other words it is necessary to satisfy the relationship V.sub.DS.gtoreq..DELTA..
On the other hand, it is necessary to satisfy the relationship V.sub.DS12.gtoreq.V.sub.GS12 -V.sub.TH12 in the n-channel MOS transistor N12. This relationship can be modified as follows: ##EQU2##
In the above expressions, V.sub.DS12, V.sub.D12, V.sub.G12, V.sub.DS13 and V.sub.G10 respectively represent a voltage between the drain and the source of the n-channel MOS transistor N12, a drain potential of the same MOS transistor, a gate potential of the same MOS transistor, a voltage between the drain and the source of the n-channel MOS transistor N13, and a gate potential of the n-channel MOS transistor N10.
In order for the n-channel MOS transistors N12 and N13 to be always in saturation areas, it is necessary to satisfy the relationship of V.sub.DS.sub.12.gtoreq..DELTA..sub.12 and V.sub.DS13.gtoreq..DELTA..sub.13, that is, V.sub.D12 (=V.sub.DS12 +V.sub.DS13).gtoreq..DELTA..sub.12 +.DELTA..sub.13. However, it is necessary to meet the following relationship V.sub.D12.gtoreq.V.sub.TH13 +.DELTA..sub.12 +.DELTA..sub.13 as described above. Therefore, this cascade current Miller circuit requires an additional voltage of V.sub.TH13. Thus, there has been known "a cascade current Miller circuit advantageous for obtaining a voltage margin" that has reduced the additionally-used voltage of V.sub.TH13.
FIG. 3 is a diagram which shows a conventional cascade current Miller circuit advantageous for obtaining a voltage margin. In FIG. 3, current paths (PASS25), (PASS20) and (PASS 21 ) and MOS transistors P20 to P23, P27, P28, N20, N21, N28 and N29 respectively correspond to (PASS12), (PASS10) and (PASS11) and the MOS transistors P10 to P13, P14, P15, N10, N11, N12 and N13 shown in FIG. 2.
The cascade current Miller circuit shown in FIG. 3 includes, in addition to the circuit structure shown in FIG. 2, a p-channel MOS transistor P24 forming a pair of current Miller circuits with the p-channel MOS transistor P20, p-channel MOS transistors P25 and P26 forming a pair of current Miller circuits, n-channel MOS transistors N22 and N24 forming a pair of current Miller circuits, n-channel MOS transistor N23 and N26 forming a pair of current Miller circuits, and n-channel MOS transistors N25 and N27 functioning as negative loads.
In the above-described structure, a current path (PASS22) is formed by the p-channel MOS transistor P24 and the n-channel MOS transistors N22 and N23, a current path (PASS23) is formed by the p-channel MOS transistor P25 and the n-channel MOS transistors N24, N25 and N26, and a current path (PASS24) is formed by the p-channel MOS transistor P26 and the n-channel MOS transistor N27.
The operation of the cascade current Miller circuit having the above-described structure advantageous for obtaining a voltage margin will be explained below. In FIG. 3, there is a relationship such that the W-size of the n-channel MOS transistor N28 is n times the W-size of the n-channel MOS transistor N20, and the W-size of the n-channel MOS transistor N29 is n times the W-size of the n-channel MOS transistor N21. Accordingly, the current flowing through the current path (PASS25) is expressed as i*n by the current Miller transfer of a current i from the current path (PASS21). Further, as the p-channel MOS transistors P20 and P22 have the same sizes, the current i flowing through the current path (PASS21) is the same as the current flowing through the current path (PASS20).
Since the p-channel MOS transistors P24 and P22 have the same sizes, the current flowing through the current path (PASS22) has the same magnitude i. Further, as the n-channel MOS transistors N23 and N26 have the same sizes, the current flowing through the n-channel MOS transistor N26 has the same magnitude i. Further, as the size ratio of the p-channel MOS transistors P25 to P26 is 1:2, a current of magnitude i/3 flows through the current path (PASS23) and a current of magnitude i*2/3 flows through the current path (PASS24).
The potential at the node Y shown in this figure will be obtained. A drain potential V.sub.D22 of the n-channel MOS transistor N22 can be expressed as follows. ##EQU3##
In this case, V.sub.TH20 and .DELTA..sub.20 represent a threshold level of the n-channel MOS transistor N20 and the above .DELTA., respectively, and V.sub.TH21 and .DELTA..sub.21 represent a threshold level of the n-channel MOS transistor N21 and the above A , respectively.
Further, the drain voltage V.sub.D22 coincides with the gate voltage V.sub.G24 of n-channel MOS transistor N24, and the drain voltage V.sub.D26 of the n-channel MOS transistor N26 can be expressed as V.sub.G24 -V.sub.GS24 -V.sub.DS25. Therefore, the following relationship is established. ##EQU4##
In this case, V.sub.GS24 and V.sub.DS25 represent a voltage between the gate and the source of the n-channel MOS transistor N24 and a voltage between the drain the source of the n-channel MOS transistor N25, respectively.
The potential of the node "Y" can be expressed as V.sub.D26 +V.sub.GS27. Therefore, the following relationship is established as a result. ##EQU5##
In this case, V.sub.DS22, V.sub.GS22, V.sub.TH22 and .DELTA..sub.22 represent a voltage between the drain and the source of the n-channel MOS transistor N22, a voltage between the gate and the source of the same MOS transistor, a threshold level of the same MOS transistor, and the above .DELTA., respectively. Further, V.sub.DS23, V.sub.GS23, V.sub.TH23 and .DELTA..sub.23 represent a voltage between the drain and the source of the n-channel MOS transistor N23, a voltage between the gate and the source of the same MOS transistor, a threshold level of the same MOS transistor, and the above A, respectively.
On the other hand, in order for the n-channel MOS transistors N28 to operate in a saturation area, it is necessary to meet the relationship of V.sub.DS28.gtoreq.V.sub.GS28 -V.sub.TH28. Therefore, the following relationship is established. ##EQU6##
In other words, the relationship of V.sub.DS28.gtoreq..DELTA..sub.20 +.DELTA..sub.21 is obtained. This corresponds to the theoretical expression of V.sub.D12 &gt;.DELTA..sub.12 +.DELTA..sub.13 obtained in the explanation of the normal cascade current Miller circuit.
Accordingly, this cascade current Miller circuit includes the above-described three current paths (PASS22), (PASS23) and (PASS24) for obtaining the above-described voltage Y, in addition to the above-described normal cascade current Miller circuit. As a result, it is possible to operate for an input of a large signal corresponding to the voltage of V.sub.TH13 shown in FIG. 2.
In the above expressions, V.sub.DS28, V.sub.GS28, V.sub.TH28, V.sub.G28 and V.sub.D28 represent a voltage between the drain and the source of the n-channel MOS transistor N28, a voltage between the gate and the source of the same MOS transistor, a threshold level of the same MOS transistor, a gate voltage and a drain voltage of the same MOS transistor, respectively. V.sub.DS29 represents a voltage between the drain and the source of the n-channel MOS transistor N29.
Further, the n-channel MOS transistor N29 has the following relationship. ##EQU7##
Thus, it is can be understood that the n-channel MOS transistor N29 is in the saturation area when V.sub.DS29.gtoreq..DELTA..sub.29.
In the above-described cascade current Miller circuit advantageous for obtaining a voltage margin shown in FIG. 3, the magnitudes of the currents flowing through the three current paths (PASS22), (PASS23) and (PASS24) are assumed as i, i/3 and i*2/3 respectively. However, as the object of the circuit is to obtain the above-described voltage Y, the magnitudes of i, i/3 and i*2/3 are not necessarily required in the above current paths. Particularly, when the other circuits do not require a large current by using this cascade current Miller circuit, the magnitudes of these currents flowing through the three current paths (PASS22), (PASS23) and (PASS24) were not optimum. Therefore, these current levels have been a cause of interrupting energy saving of the circuit.